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dc.contributor.authorTalebiyan, S. Reza
dc.contributor.authorHosseini-Khayat, Saied
dc.date.accessioned2016-01-21T13:03:42Z
dc.date.available2016-01-21T13:03:42Z
dc.date.issued2009
dc.identifier.urihttp://10.11.10.50/xmlui/handle/123456789/3925
dc.descriptionThe annals of "Dunarea de Jos" University od Galatien_US
dc.description.abstractPipeline FFT processors are used in mobile communication systems and in particular in OFDM-based systems. This paper presents a method for power analysis of pipeline FFT processors. This method applies to various architectures with different radices. It also presents a method for mapping utilization rate onto clock-gating, which results in efficient power consumption.en_US
dc.language.isoenen_US
dc.publisher"Dunarea de Jos" University of Galatien_US
dc.subjectPipeline FFT processoren_US
dc.subjectutilization rateen_US
dc.subjectpower analysisen_US
dc.subjectclock-gatingen_US
dc.titlePower Estimation of Pipeline FFT Processorsen_US
dc.typeArticleen_US


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