Power Estimation of Pipeline FFT Processors

dc.contributor.author	Talebiyan, S. Reza
dc.contributor.author	Hosseini-Khayat, Saied
dc.date.accessioned	2016-01-21T13:03:42Z
dc.date.available	2016-01-21T13:03:42Z
dc.date.issued	2009
dc.identifier.uri	http://10.11.10.50/xmlui/handle/123456789/3925
dc.description	The annals of "Dunarea de Jos" University od Galati	en_US
dc.description.abstract	Pipeline FFT processors are used in mobile communication systems and in particular in OFDM-based systems. This paper presents a method for power analysis of pipeline FFT processors. This method applies to various architectures with different radices. It also presents a method for mapping utilization rate onto clock-gating, which results in efficient power consumption.	en_US
dc.language.iso	en	en_US
dc.publisher	"Dunarea de Jos" University of Galati	en_US
dc.subject	Pipeline FFT processor	en_US
dc.subject	utilization rate	en_US
dc.subject	power analysis	en_US
dc.subject	clock-gating	en_US
dc.title	Power Estimation of Pipeline FFT Processors	en_US
dc.type	Article	en_US